Uncategorized – Electronic Design

FIR (Finite impulse response) filter

Overview

Finite impulse response (FIR) filters are characterized by the fact that they use only delayed versions of the input signal to filter the input to the output.
For a causal discrete-time FIR filter of order N, each value of the output sequence is a weighted sum of the most recent input values:

Where:

x[n] is the input signal,
y[n] is the output signal,
N is the filter order
bi is the value of the impulse response, also a coefficient of the filter

Filter design

FIR filter designing is finding the coefficients and filter order that meet certain specifications. When a particular frequency response is desired, several different design methods are common:

Window design method
Frequency sampling method
Least MSE (mean square error) method
Parks-McClellan method
DFT algorithms

There many software such as MATLAB, GNU Octave, Scilab and SciPy (Python).
In this topic, I only share how to implement FIR filter on FPGA. So the detail of filter designing, finding coefficients will shared in the later topics.

Implementing a FIR filter on FPGA for slow signal

FIR filter for slow signal will designed by using special way to save the number of multipliers.

Finding coefficients using window method

Using Python

from future import print_function
from future import division
import numpy as np

fS = 48000 # Sampling rate.
fL = 22000 # Cutoff frequency.
N = 13 # Filter length, must be odd.

h = np.sinc(2 * fL / fS * (np.arange(N) – (N – 1) / 2))

h /= np.sum(h)
print(h)

2. Implementing on FPGA

(Finite-state machine with datapath of slow FIR filter)

(Simulation result – using Python + QuestaSim)

Audio DAC is classified to:
- R2R ladder
- Delta-Sigma 1 bit
- Delta-Sigma multi-bit
The basic of R-2R resistor ladder DAC

The R-2R resistor ladder network directly converts a parallel digital symbol/word into an analog voltage

(24 bit R-2R resistor ladder)

The R–2R network causes these digital bits to be weighted in their contribution to the output voltage V_out. Depending on which bits are set to 1 and which to 0, the output voltage (V_out) will have a corresponding stepped value between 0 and V_ref minus the value of the minimal step, corresponding to bit 0. The actual value of V_ref (and the voltage of logic 0) will depend on the type of technology used to generate the digital signals.

For a digital value VAL, of a R–2R DAC with N bits and 0 V/V_ref logic levels, the output voltage V_out is:

Vout = Vref * VAL / 2^N

3. Digital Design (Verilog) FPGA-based R-2R resistor ladder DAC

(R-2R DAC block diagram)

(R-2R DAC RTL diagram – Quartus Software)

I2S Receiver module:

The I2S protocol is a common standard used to send audio data. It is a serial protocol very similar to SPI, but it is a streaming protocol. That means it is always transmitting data. I2S sends a stream of stereo audio data. For each audio sample there is a left channel and a right channel value. The values can be any number of bits, although 16, 20, 24, and 32 bit values are the most common

(I2S Protocol timing diagram)

Clock Control Module:

This module includes sampling rate detect and PLL module.

Sampling rate detect operates base on the period of Word Clock of I2S (WS) to determines the sampling rate of I2S. It will be 44.1khz, 88.2khz, 176.4khz, 352.8khz… or 48khz, 96khz, 192khz, 384khz, 768khz. Then this module will choose suitable input OSC (49.152Mhz or 45.1584Mhz) to feed to PLL module.

(Detect sampling rate module RTL diagram – Quartus Software)

PLL module uses external clock that is choose to generate few internal clocks. These clocks are used for oversampling clocks, filter clocks, R-2R transmitter clocks

(PLL module RTL diagram – Quartus Software)

Interpolation filter module:

Digital data transmitter:

Digital data transmitter module receives data from Interpolation filter module, converts digital data from single-end to balanced data and transmits R2R driver module (Altera Max V CPLD)

Data transmit protocol is my protocol, it is not standard protocol. It is a bit stream protocol and Left / Right are transmitted separately.

(Digital data transmitter RTL diagram – Quartus Software)

4. PCB Design FPGA-based R-2R resistor ladder DAC

PCB includes 2 parts : FPGA using Altera Cyclone IV and CPLD using Altera MAX V

FPGA Part

FPGA Part uses Altera Cyclone IV EP4CE6 – 144TQFP package

Oscillators use CRYSTEK CCHD-957. Crystek’s Model CCHD-957 HCMOS CLOCK oscillator family has been designed specifically for High Definition Audio (HD Audio). It features a typical low close-in phase noise of -100 dBc/Hz @ 10 Hz offset, and a noise floor of -169 dBc/Hz. With this extreme low phase noise performance, you will “Hear the Difference”.

Datasheet: https://www.crystek.com/crystal/spec-sheets/clock/CCHD-957.pdf